1. Field of the Invention
This invention relates to an organic light emitting diode, and more particularly to an organic light emitting diode display device that is adaptive for reducing the number of power lines in an organic light emitting diode panel to thereby increase the aperture ratio of the display device as well as improve brightness.
2. Description of the Related Art
Recently, there have been highlighted various flat panel display devices reduced in weight and bulk that are capable of eliminating disadvantages of a cathode ray tube (CRT). Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and a light emitting diode (LED) display, etc.
The LED display device among such display devices employs an LED capable of light-emitting a phosphorous material by a re-combination of electrons with holes. The LED display device is generally classified into an inorganic LED device using an inorganic compound as the phosphorous material, and an organic LED (OLED) device using an organic compound as the phosphorous material. Such an OLED display device has been highlighted into a post-generation display device because it has advantages of a low voltage driving, a self-luminescence, a thin thickness, a wide viewing angle, a fast response speed and a high contrast, etc.
The OLED as a light emitting device usually includes an electron injection layer, an electron carrier layer, a light-emitting layer, a hole carrier layer and a hole injection layer that are disposed between a cathode and an anode of a light emitting diode. In such an OLED, when a predetermined voltage is applied between the anode and the cathode, electrons produced from the cathode are moved, via the electron injection layer and the electron carrier layer, into the light-emitting layer while holes produced from the anode are moved, via the hole injection layer and the hole carrier layer, into the light-emitting layer. Thus, the electrons and the holes fed from the electron carrier layer and the hole carrier layer emit a light by their re-combination at the light-emitting layer.
As shown in FIG. 1, an active matrix OLED display device employing the above-mentioned OLED includes an OLED panel 13 having n×m pixels P[i,j] arranged in a matrix type at each area defined by intersections between n gate lines G1 to Gn (wherein n is an integer) and m data lines D1 to Dm (wherein m is an integer), a gate driving circuit 12 for driving the gate lines G1 to Gn, a data driving circuit 11 for driving the data lines D1 to Dm, and m power voltage supply lines S1 to Sm arranged in parallel to the data lines D1 to Dm to supply a high-level power supply voltage VDD to each pixel P[i,j]. Herein, P[i,j] is a pixel positioned at an ith row and a jth column, wherein i is an integer smaller than or equal to n, and j is an integer smaller than or equal to m.
The gate driving circuit 12 supplies a scanning signal to the gate lines G1 to Gn to sequentially drive the gate lines G1 to Gn.
The data driving circuit 11 converts a digital data voltage inputted from the exterior thereof into an analog data voltage. Further, the data driving circuit 12 supplies the analog data voltage to the data lines D1 to Dm whenever the scanning signal is applied.
Each of the pixel P[i,j] receives a data voltage from the jth data line Dj whenever a scanning signal is applied to the ith gate line Gi, and generates a light corresponding to the data voltage.
To this end, each pixel P[i,j] includes an OLED having an anode connected to the jth power voltage supply line Sj, and an OLED driving circuit 15 connected to a cathode of the OLED to drive the OLED and the ith gate line G1 and the jth data line Dj to supply a low-level power supply voltage VSS.
The OLED driving circuit 15 includes a first transistor T1 for supplying a data voltage from the jth data line to a first node N1, a second transistor T2 for controlling an amount of current flowing at the OLED in response to a voltage at the first node N1, and a storage capacitor Cs in which the voltage at the first node N1 is charged.
The first transistor T is turned on when a scanning signal is applied, via the gate line Gi, thereto, so that it supplies a data voltage from the data line Dj to the first node N1. The data voltage supplied to the first node N1 is charged in the storage capacitor Cs and is supplied to a gate electrode of the second transistor T2. If the second transistor T2 is turned on by the data voltage supplied in this manner, then a current flows through the OLED. At this time, the current flowing through the OLED is generated by the high-level power supply voltage VDD from the jth power voltage supply line Sj, and an amount of the generated current is in proportion to a magnitude of the data voltage applied to the second transistor T2. Further, even when the first transistor T1 is turned off, the second transistor T2 is maintained at the turned-on state by a voltage at the first node N1 derived by the storage capacitor Cs charged with the data voltage to thereby control an amount of current flowing through the OLED until a data voltage at the next frame is supplied thereto.
Meanwhile, the above-mentioned OLED display device has the following problems.
As shown in FIG. 1, the OLED panel is provided with the power voltage supply line Sj for supplying the high-level power supply voltage VDD to each pixel. For instance, the OLED panel is provided with 800 power voltage supply lines Sj in the case of SVGA having a resolution of 800×600 while being provided with 1024 power voltage supply lines Sj in the case of XGA having a resolution of 1024×768. However, such a large number of the power voltage supply lines reduces an aperture ratio of the OLED panel and deteriorates brightness. It also can increase the cost and size of the OLED panel.